What A/d Registers Should Be Configured For This Lab?

3.nine Analog Modules

The A/D converter module has the post-obit features:

• The converter generates a 10-scrap binary result using the method of successive approximation and stores the conversion results into the ADC registers (ADRESL and ADRESH);
• There are 14 separate analog inputs;
• The A/D converter converts an analog input signal into a 10-bit binary number;
• The minimum resolution or quality of conversion may be adjusted to various needs by selecting voltage references Vref- and Vref+.

A/D CONVERTER

Even though the use of A/D converter seems to be very complicated, it is basically very simple, simpler than using timers and serial communication module, anyhow.

The performance of A/D converter is in command of the bits of four registers:

• ADRESH Contains high byte of conversion result;
• ADRESL Contains low byte of conversion result;
• ADCON0 Control annals 0; and
• ADCON1 Command register 1.

ADRESH and ADRESL Registers

The result obtained later on converting an analog value into digital is a10-bit number that is to exist stored in the ADRESH and ADRESL registers. At that place are two ways of handling it - left and right justification which simplifies its use to a smashing extent. The format of conversion outcome depends on the ADFM bit of the ADCON1 register. In the event that the A/D converter is non used, these registers may be used as full general-purpose registers.

A/D ACQUISITION REQUIREMENTS

In order to enable the ADC to see its specified accuracy, it is necessary to provide a certain time delay between selecting specific analog input and measurement itself. This time is chosen 'acquisition time' and mainly depends on the source impedance. There is an equation used to calculate this time accurately, which in the worst example amounts to approximately 20uS. So, if you want the conversion to be authentic, don't forget this important item.

ADC CLOCK Flow

The time needed to complete a one-flake conversion is divers every bit TAD. It is required to be at least 1,half-dozen u.s.. One total x-bit A/D conversion is slightly longer than expected and amounts to eleven TAD periods. Since both clock frequency and source of A/D conversion are specified past software, it is necessary to select one of the available combinations of bits ADCS1 and ADCS0 earlier the voltage measurement on some of the analog inputs starts. These bits are stored in the ADCON0 annals.

ADC CLOCK SOURCE	ADCS1	ADCS0	DEVICE FREQUENCY (FOSC)
			20 Mhz	8 Mhz	4 Mhz	ane Mhz
Fosc/2	0	0	100 nS	250 nS	500 nS	ii u.s.a.
Fosc/eight	0	i	400 nS	i uS	2 united states	eight uS
Fosc/32	1	0	ane.6 us	4 u.s.a.	8 united states of america	32 uS
Frc	1	ane	two - 6 uS	2 - 6 us	2 - 6 united states	2 - six u.s.a.

Any change in the system clock frequency will touch the ADC clock frequency, which may adversely affect the ADC result. Device frequency characteristics are shown in the table in a higher place. The values in the shaded cells are outside of the range recommended.

HOW TO USE THE A/D CONVERTER?

In lodge to enable the A/D converter to run without problems as well as to avert unexpected results, it is necessary to consider the following:

• A/D converter does not differ between digital and analog signals. In guild to avoid errors in measurement or fleck damage, pins should be configured as analog inputs earlier the procedure of conversion starts. $.25 used for this purpose are stored in the TRIS and ANSEL (ANSELH) registers;
• When reading the port with analog inputs, the state of the respective bits will be read as a logic zip (0); and
• Roughly speaking, voltage measurement in the converter is based on comparing input voltage with internal scale which has 1024 marks (ii¹⁰ = 1024). The lowest scale mark stands for the Vref- voltage, whilst its highest mark stands for the Vref+ voltage. Figure beneath shows selectable voltage references too every bit their minimum and maximum values.

ADCON0 Register

ADCS1, ADCS0 - A/D Conversion Clock Select $.25 select clock frequency used for internal synchronization of A/D converter. Information technology also affects duration of conversion.

ADCS1	ADCS2	CLOCK
0	0	Fosc/2
0	1	Fosc/8
1	0	Fosc/32
1	1	RC *

* Clock is generated by internal oscillator which is congenital in the converter. CHS3-CHS0 - Analog Channel Select bits select a pin or an analog aqueduct for A/D conversion, i.e. voltage measurement:

CHS3	CHS2	CHS1	CHS0	CHANNEL	Pin
0	0	0	0	0	RA0/AN0
0	0	0	one	ane	RA1/AN1
0	0	1	0	2	RA2/AN2
0	0	1	1	3	RA3/AN3
0	1	0	0	4	RA5/AN4
0	1	0	i	five	RE0/AN5
0	ane	i	0	6	RE1/AN6
0	one	1	1	7	RE2/AN7
1	0	0	0	viii	RB2/AN8
i	0	0	i	nine	RB3/AN9
ane	0	1	0	x	RB1/AN10
i	0	1	1	eleven	RB4/AN11
i	1	0	0	12	RB0/AN12
i	1	0	1	13	RB5/AN13
i	i	ane	0	CVref
1	1	one	one	Vref = 0.6V

Become/DONE - A/D Conversion Status bit determines electric current status of conversion:

• 1 - A/D conversion is in progress.
• 0 - A/D conversion is complete. This chip is automatically cleared by hardware when the A/D conversion is complete.

ADON - A/D On fleck enables A/D converter.

• i - A/D converter is enabled.
• 0 - A/D converter is disabled.

Let'south do it in mikroC...

/* This example code reads analog value from aqueduct two and displays it on PORTB and PORTC as 10-fleck binary number.*/  #include <built_in.h> unsigned int adc_rd;  void principal() {     ANSEL = 0x04;               // Configure AN2 as analog pin     TRISA = 0xFF;               // PORTA is configured equally input     ANSELH = 0;                 // Configure all other AN pins as digital I/O     TRISC = 0x3F;               // Pins RC7 and RC6 are configured as outputs     TRISB = 0;                  // PORTB is configured as an output          do {         temp_res = ADC_Read(two); // Get x-chip issue of AD conversion         PORTB = temp_res;       // Send lower 8 bits to PORTB         PORTC = temp_res >> 2;  // Transport two most significant $.25 to RC7, RC6     } while(1);                 // Remain in the loop }

ADCON1 Annals

ADFM - A/D Upshot Format Select bit

• one - Conversion outcome is right justified. Six most significant $.25 of the ADRESH are not used.
• 0 - Conversion result is left justified. Half-dozen least significant bits of the ADRESL are not used.

VCFG1 - Voltage Reference bit selects negative voltage reference source needed for the operation of A/D converter.

• 1 - Negative voltage reference is practical to the Vref- pin.
• 0 - Power supply voltage Vss is used as negative voltage reference source.

VCFG0 - Voltage Reference chip selects positive voltage reference source needed for the functioning of A/D converter.

• 1 - Positive voltage reference is applied to the Vref+ pin.
• 0 - Power supply voltage Vdd is used as positive voltage reference source.

In Short

In guild to measure voltage on an input pin past the A/D converter, the following should be washed: Step 1 - Port configuration:

• Write a logic 1 (1) to a bit of the TRIS register, thus configuring the appropriate pin as an input.
• Write a logic one (one) to a bit of the ANSEL register, thus configuring the advisable pin as an analog input.

Step 2 - ADC module configuration:

• Configure voltage reference in the ADCON1 register.
• Select ADC conversion clock in the ADCON0 annals.
• Select one of input channels CH0-CH13 of the ADCON0 register.
• Select data format using the ADFM scrap of the ADCON1 register.
• Enable A/D converter by setting the ADON scrap of the ADCON0 annals.

Step three - ADC interrupt configuration (optionally):

• Clear the ADIF flake.
• Set the ADIE, PEIE and GIE bits.

Step iv - Await for the required acquisition time to laissez passer (approximately 20uS). Step v - Offset conversion by setting the Get/DONE bit of the ADCON0 register. Step 6 - Wait for ADC conversion to complete.

• It is necessary to check in the program loop whether the GO/Washed pin is cleared or await for an A/D interrupt (must exist previously enabled).

Step seven - Read ADC results:

• Read the ADRESH and ADRESL registers.

ANALOG COMPARATOR

In add-on to A/D converter, in that location is another module, which until quite recently has been embedded only in integrated circuits belonging to the so called analog electronics. Owing to the fact that it is hardly possible to discover any more complex automatic device which in some way does non use these circuits, two high quality comparators, along with additional electronics, are integrated into the microcontroller and connected to its pins. How does a comparator operate? Basically, the analog comparator is an amplifier which compares the magnitude of voltages at two inputs. Information technology has two inputs and ane output. Depending on which input has a college voltage (analog value), a logic zero (0) or logic one (one) (digital values) will appear on its output:

• When the analog voltage at Vin- is higher than that at Vin+, the output of the comparator is a digital low level.
• When the analog voltage at Vin+ is college than that at Vin-, the output of the comparator is a digital high level.

The PIC16F887 microcontroller has 2 such voltage comparators the inputs of which are connected to I/O pins RA0-RA3, whereas the outputs are connected to the RA4 and RA5 pins. There is also a voltage reference internal source on the chip itself, which will be discussed subsequently. These 2 circuits are under control of the bits stored in the post-obit registers:

• CM1CON0 is in control of comparator C1;
• CM2CON0 is in control of comparator C2;
• CM2CON1 is in control of comparator C2;

VOLTAGE REFERENCE INTERNAL SOURCE

Ane of 2 analog voltages provided on the comparator inputs is unremarkably stable and unchangeable. Information technology is called 'voltage reference'(Vref). To generate it, both external and special internal voltage source tin can exist used. When the voltage source is selected, Vref is derived from information technology by means of a ladder network consisting of 16 resistors which grade a voltage divider. The voltage source is selectable through the both ends of the divider by the VRSS bit of the VRCON register. In add-on, the voltage fraction provided past the resistor ladder network may be selected through the $.25 VR0-VR3 and used every bit a voltage reference. See figure below.

The comparator voltage reference has two ranges each containing 16 voltage levels. Range selection is controlled past the VRR fleck of the VRCON register. The selected voltage reference CVref may exist output to the RA2/AN2 pin. Even though the main idea was to obtain varying voltage reference for the functioning of analog modules, a simple A/D converter is obtained thereby likewise. This converter is very useful in some situations. Its operation is under command of the VRCON register.

COMPARATORS AND INTERRUPT

Every change of the logic state of any comparator'due south output causes the flag bit CMIF of the annals PIR to be set. Such changes will also cause an interrupt if the post-obit bits are prepare:

• The CMIE bit of the PIE register = 1;
• The PEIE bit of the INTCON annals = 1; and
• The GIE scrap of the INTCON register = 1.

If an interrupt is enabled, whatever change on the comparator'south output when the microcontroller is ready in Slumber mode can cause the microcontroller to exit that mode and proceed with normal operation.

Functioning DURING Slumber

The comparator, if enabled earlier entering the Sleep style, remains active during Sleep. If the comparator is not used to wake up the device, power consumption tin be minimized in the Slumber mode by turning the comparator off. It is performed past clearing the CxON bit of the CMxCON0 register. To enable the comparator to wake upwardly the microcontroller from sleep, the CxIE bit of the IE2 register and the PEIE bit of the INTCON register must exist set up. The instruction following the Sleep instruction is ever executed after exiting the Sleep style. If the GIE fleck of the INTCON register is gear up, the device will execute the Interrupt Service Routine.

CM1CON0 Annals

Bits of this register are in control of the comparator C1. It mainly affects the configuration of its inputs. To understand information technology better, look at figure below which shows just a part of electronics directly affected by the $.25 of this register.

C1ON - Comparator C1 Enable bit enables comparator C1.

• 1 - Comparator C1 is enabled.
• 0 - Comparator C1 is disabled.

C1OUT - Comparator C1 Output flake is the output of the comparator C1. If C1POL = 1 (comparator output is inverted)

• 1 - Analog voltage at C1Vin+ is lower than analog voltage at C1Vin-.
• 0 - Analog voltage at C1Vin+ is higher than analog voltage at C1Vin-.

If C1POL = 0 (comparator output is not-inverted)

• 1 - Analog voltage at C1Vin+ is higher than analog voltage at C1Vin-.
• 0 - Analog voltage at C1Vin+ is lower than analog voltage at C1Vin-.

C1OE Comparator C1 Output Enable bit.

• 1 - Comparator C1OUT output is connected to the C1OUT pin.*
• 0 - Comparator output is internal merely.

* In order to enable the C1OUT bit to be present on the pin, two conditions must be met: C1ON = i (comparator must be on) and the corresponding TRIS flake = 0 (pin must be configured as an output).

C1POL - Comparator C1 Output Polarity Select bit enables the country of the comparator C1 output to be inverted.

• 1 - Comparator C1 output is inverted.
• 0 - Comparator C1 output is non-inverted.

C1R - Comparator C1 Reference Select flake

• 1 - Non-inverting input C1Vin+ is continued to the reference voltage C1Vref.
• 0 - Non-inverting input C1Vin+ is continued to the C1IN+ pivot.

C1CH1, C1CH0 - Comparator C1 Channel Select chip

C1CH1	C1CH0	COMPARATOR C1VIN- INPUT
0	0	Input C1Vin- is connected to the C12IN0- pivot
0	1	Input C1Vin- is connected to the C12IN1- pin
1	0	Input C1Vin- is connected to the C12IN2- pin
ane	1	Input C1Vin- is connected to the C12IN3- pin

CM2CON0 Register

$.25 of this register are in control of the comparator C2. Similar to the previous instance, figure below shows a simplified schematic of the circuit affected by the bits of this register.

C2ON - Comparator C2 Enable flake enables comparator C2.

• 1 - Comparator C2 is enabled; and
• 0 - Comparator C2 is disabled.

C2OUT - Comparator C2 Output scrap is the output of the comparator C2. If C2POL = ane (comparator output inverted)

• 1 - Analog voltage at C1Vin+ is lower than analog voltage at C1Vin-.
• 0 - Analog voltage at C1Vin+ is higher than analog voltage at C1Vin-.

If C2POL = 0 (comparator output not-inverted)

• 1 - Analog voltage at C1Vin+ is higher than analog voltage at C1Vin-.
• 0 - Analog voltage at C1Vin+ is lower than analog voltage at C1Vin-.

C2OE - Comparator C2Output Enable bit

• i - Comparator C2OUT output is continued to the C2OUT pin.*
• 0 - Comparator output is internal only.

* In order to enable the C2OUT bit to be present on the pin, two conditions must be met: C2ON = 1 (comparator must exist on) and the corresponding TRIS bit = 0 (pin must be configured as an output).

C2POL - Comparator C2 Output Polarity Select scrap enables the state of the comparator C2 output to exist inverted.

• 1 - Comparator C2 output is inverted.
• 0 - Comparator C2 output is non-inverted.

C2R - Comparator C2 Reference Select bit

• one - Non-inverting input C2Vin+ is connected to the reference voltage C2Vref.
• 0 - Not-inverting input C2Vin+ is connected to the C2IN+ pivot.

C2CH1, C2CH0 Comparator C2 Aqueduct Select bit

C2CH1	C2CH0	COMPARATOR C2VIN- INPUT
0	0	Input C2Vin- is connected to the C12IN0- pin
0	1	Input C2Vin- is continued to the C12IN1- pin
1	0	Input C2Vin- is connected to the C12IN2- pin
ane	1	Input C2Vin- is connected to the C12IN3- pin

CM2CON1 Register

MC1OUT Mirror Re-create of C1OUT fleck MC2OUT Mirror Re-create of C2OUT bit C1RSEL Comparator C1 Reference Select bit

• ane - Selectable voltage CVref is used in the voltage reference C1Vref source.
• 0 - Fixed voltage reference 0.6V is used in the voltage reference C1Vref source.

C2RSEL - Comparator C2 Reference Select bit

• i - Selectable voltage CVref is used in the voltage reference C2Vref source.
• 0 - Fixed voltage reference 0.6V is used in the voltage reference C2Vref source.

T1GSS - Timer1 Gate Source Select chip

• 1 - Timer T1gate source is T1G.
• 0 - Timer T1gate source is SYNCC2OUT.

C2SYNC - Comparator C2 Output Synchronization chip

• ane - Comparator C2 output is synchronized to the falling edge of Timer TMR1 clock.
• 0 - Comparator output is asynchronous signal.

VRCON Register

VREN Comparator C1 Voltage Reference Enable chip

• 1 - Voltage reference CVref source is powered on.
• 0 - Voltage reference CVref source is powered off.

VROE Comparator C2 Voltage Reference Enable scrap

• 1 - Voltage reference CVref is continued to the pin.
• 0 - Voltage reference CVref is disconnected from the pivot.

VRR - CVref Range Choice bit

• ane - Voltage reference source is set to low range.
• 0 - Voltage reference source is set to loftier range.

VRSS - Comparator Vref Range selection bit

• i - Voltage reference source is in the range of Vref+ to Vref-.
• 0 - Voltage reference source is in the range of Vdd to Vss (ability supply voltage).

VR3 - VR0 CVref Value Selection If VRR = 1 (low range) Voltage reference is calculated using the formula: CVref = ([VR3:VR0]/24)Vdd If VRR = 0 (high range) Voltage reference is calculated using the formula: CVref = Vdd/iv + ([VR3:VR0]/32)Vdds

In Brusk

In gild to properly use born comparators, it is necessary to practice the following: Stride 1 - Module Configuration:

• In lodge to select the advisable mode, $.25 of the CM1CON0 and CM2CON0 registers should be configured. Interrupt should be disabled on any modify of mode.

Step ii - Internal voltage reference Vref source configuration (only when used). In the VRCON register it is necessary to:

• Select one of two voltage ranges using the VRR fleck.
• Configure necessary Vref using bits VR3 - VR0.
• Fix the VROE scrap if needed.
• Enable voltage Vref source by setting the VREN flake.

Formula used to summate voltage reference: VRR = 1 (depression range) CVref = ([VR3:VR0]/24)VLADDER VRR = 0 (high range) CVref = (VLADDER/four) + ([VR3:VR0]VLADDER/32) Vladder = Vdd or ([Vref+] - [Vref-]) or Vref+ Pace 3 - Start of operation:

• Enable an interrupt by setting bits CMIE (PIE register), PEIE and GIE (INTCON annals).
• Read the C1OUT and C2OUT $.25 of the CMCON register.
• Read the CMIF flag bit of the PIR register. Later on being set, this scrap must exist cleared in software.

In social club to synchronize all the processes taking place inside the microcontroller, a clock signal must exist used, while in order to generate the clock bespeak, a clock oscillator must exist used. As simple as that. This microcontroller has several oscillators capable of working in unlike modes and this is where the story becomes interesting...

Source: https://www.mikroe.com/ebooks/pic-microcontrollers-programming-in-c/analog-modules

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